1. Field of the Invention
The present invention relates to a frequency synthesizer, and more particularly, to a synthesizer capable of reducing jitter noise and suitable for high accuracy frequency synthesizing.
2. Description of the Prior Art
Frequency synthesizer is a device for performing frequency synthesizing, so as to output specific frequency. Common frequency synthesizer adopts the structure of sigma-delta modulating and is realized in analog method.
Please refer to FIG. 1, which is a schematic diagram of a conventional frequency synthesizer 10 with a sigma-delta modulating structure. The frequency synthesizer 10 includes a phase-locked loop 102, a frequency divider 104, and a sigma-delta modulator 106. The phase-locked loop 102 generates an output signal SO according to a reference signal SREF and a feedback signal SF. The sigma-delta modulator 106 is utilized for controlling the frequency dividing ratio of the frequency divider 104. However, the frequency synthesizer 10 of the sigma-delta modulating structure utilizes the concept of averaging frequency for acquiring the required signal frequency and the accuracy of the frequency divider 104 is determined based on the length of the output signal SO. The speed of phase locking may be slow if the accuracy of the frequency divider 104 is insufficient. In such a condition, the cost would be significantly higher for achieving an acceptable performance.
On the other hand, the variations of signals are tremendous when the sigma-delta modulator 106 modulates the frequency dividing ratio of the frequency divider 104. Thus, significant variations of the frequency dividing ratio generate considerable jitter noise. For example, assume the reference frequency FR is the frequency of the reference signal SREF and the frequency FO is the frequency of the output signal SO. If the required output frequency FO is 5.3 times the reference frequency FR (FO=5.3FR), the sigma-delta modulator 106 controls the frequency divider 104 to selectively perform the frequency dividing procedure of 5 times and 6 times for acquiring the output signal SO with an average frequency equaling 5.3 times the reference frequency FR. In such a condition, the signal variation margin reaches 20%, which results in significant jitter noise. The phase-locked loop 102 therefore needs to configure greater capacitor for filtering jitter noise. However, the configuration of the greater capacitor can lead to slower reaction speed and greater area of the integrated chip. The manufacture cost is therefore increased.